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the mcf5206e integrated microprocessor combines a coldfire ? core with several peripheral functions such as a dram controller, timers, parallel and serial interfaces, and system integration. this device is an enhanced version of the mcf5206, which is in production today. not only does the mcf5206e provide a performance upgrade to the mcf5206 due to the increased 4-kbyte i-cache, 8-kbyte sram and increased frequency, but this device also integrates an additional multiply accumulate (mac) unit, hardware divide, and two-channel dma to the device while maintaining pin compatibility with the mcf5206. the revolutionary coldfire architecture gives cost-sensitive, high-volume markets new levels of price and performance. based upon the concept of variable-length risc technology, the coldfire core combines the architectural simplicity of conventional 32-bit risc with a memory-saving, variable-length instruction set. in de ning the coldfire architecture for embedded processing applications, motorola incorporated risc architecture for peak performance and a simpli ed version of the variable-length instruction set found in the m68000 family for code density. by using a variable-length instruction set architecture, embedded processor designers using coldfire processors will enjoy signi cant system-level advantages over conventional xed-length risc architectures. the denser binary code for coldfire uses less memory than xed-length instruction processors available. this improved code density means more ef cient system memory usage for a given application, and allows for slower, less costly memory to help achieve a target price/performance level for embedded processing applications. the mcf5206e version 2 core delivers enhanced performance while maintaining low system costs. the addition of a mac module and hardware divide to the core increases performance of complex arithmetic functions normally used in dsp applications. to speed program execution, the on chip instruction cache and sram provides one-cycle access to critical code and data. the mcf5206e processor greatly reduces the time required for system design and implementation by packaging common system functions on chip and providing glueless interfaces to 8 bit, 16 bit and 32 bit dram, sram, rom and i/o devices. the integrated peripheral functions provide high performance and exibility. the dram controller supports up to 512 mbytes of dram. the mcf5206e processor supports both fast page-mode and extended-data-out drams. the dma controller provides two fully programmable channels that support both single and dual addressing modes. the serial interfaces consists of two independent uarts and a separate i 2 c-compatible 1 motorola bus (m-bus interface). two 16-bit general-purpose multimode timers provide separate input and output signals. for system protection, the processor includes a programmable 16-bit software product brief MCF5206EPB/d rev. 2.1, 3/2002 mcf5206e integrated coldfire ? microprocessor product brief f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2 mcf5206e integrated coldfire?microprocessor product brief motorola mcf5206e overview watchdog timer and several bus monitors. in addition, common system functions such as chip-selects, interrupt control, bus arbitration and ieee 1149.1 test (jtag) support are included. a sophisticated debug interface supports both background-debug mode and real-time trace. the interface is common to all coldfire-based processors and allows emulator support across the entire coldfire family. 1.1 mcf5206e overview this section gives a brief overview of the mcf5206e processor. figure 1 is a block diagram of the mcf5206e processor. . figure 1. mcf5206e block diagram 1.1.1 features list the following are the primary features of the mcf5206e integrated processor: coldfire version 2 core ? variable-length risc ? 32-bit internal address bus with 28-bit external bus; chip select and dram decoding use internal 32 bit ? 32-bit data base clock jtag 4kbyte icache dram controller chip interrupt controller external bus interface parallel port duart timers m-bus module dma controller 8kbyte sram debug module coldfire mac core h/w divide system bus selects controller clock input jtag interface interface bom dram control chip selects interrupt support external bus parallel interface serial interface timer support m-bus interface dma control f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mcf5206e integrated coldfire?microprocessor product brief 3 mcf5206e overview ? 16 user-visible 32-bit wide registers ? supervisor and user modes for system protection ? vector base register to relocate exception-vector table ? optimized for high level language constructs ? 50 mips at 54 mhz multiply accumulate ? high speed, complex arithmetic functions for signal processing applications ? single clock issue rate with 3-stage execution pipeline ? one mac cycle for 16x16 and 32x32 multiplies, all with 32-bit accumulate ? four-kbyte direct-mapped instruction cache ? eight-kbyte on-chip sram that provides one-cycle access to critical code and data dram controller ? programmable refresh timer provides cas before ras refresh ? support for 2 separate memory banks ? support for fast page mode drams and extended-data-out (edo) drams ? external bus master access dma controller ? two fully programmable channels with external request pins supporting dual-address and single address transfers with 32-bit capability ? two address pointers per channel that can increment or remain constant ? 16-bit transfer counter per channel ? operand packing and unpacking ? auto-alignment transfers for ef cient block movement ? bursting and cycle stealing ? two clock-cycle internal access two universal synchronous/asynchronous receiver/transmitters (uarts) ? full duplex operation ? baud-rate generator ? modem control signals (cts , r ts ) ? processor-interrupt capability dual 16-bit general-purpose multimode timers ? 8-bit prescaler ? timer input and output pins ? 12 ns resolution with 54 mhz system clock ? processor interrupt capability motorola bus (m-bus) module ? interchip bus interface for eeproms, lcd controllers, a/d converters, keypads ? compatible with industry-standard i 2 c bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4 mcf5206e integrated coldfire?microprocessor product brief motorola mcf5206e overview ? master or slave modes supporting multiple masters ? automatic interrupt generation with programmable level system interface ? glueless bus interface to 8 bit, 16 bit, and 32 bit dram, sram, rom, and i/o devices ? eight programmable chip selects and programmable wait states and port sizes allowing external bus masters to access chip selects ? programmable external interrupts ? 8-bit general-purpose i/o interface ? system protection ? 16-bit software watchdog timer with prescaler ? double bus fault monitor ? bus timeout monitor ? spurious interrupt monitor ? programmable interrupt controller (low interrupt latency, 3 external interrupt inputs, and programmable interrupt priority and autovector generator) ? ieee 1149.1 test (jtag) support system debug interface ? real-time trace ? background debug mode (bdm) fully static 3.3-volt operation with 5-volt tolerant inputs 160-pin qfp package; pin-compatible with mcf5206 1.1.2 coldfire version 2 core the coldfire processor core consists of two independent, decoupled pipeline structures that maximize performance while minimizing core size. the instruction fetch pipeline (ifp) is a two-stage pipeline for prefetching instructions. the prefetched instruction stream is then gated into the two-stage operand execution pipeline (oep), which decodes the instruction, fetches the required operands and then executes the required function. the ifp and oep pipelines are decoupled by an instruction buffer that serves as a fifo queue, the ifp can prefetch instructions in advance of their actual use by the oep, thereby minimizing time stalled waiting for instructions. the oep is implemented in a two-stage pipeline featuring a traditional risc datapath with a dual-read-ported register le feeding an arithmetic/logic unit. 1.1.3 instruction cache the instruction cache improves system performance by providing cached instructions to the execution unit in a single clock. the mcf5206e processor uses a 4-kbyte, direct-mapped instruction cache to achieve 50 mips at 54 mhz. the cache is accessed by physical addresses, where each 16-byte line consists of an address tag and a valid bit. the instruction cache also includes a bursting interface for 32-bit, 16-bit, and 8-bit port sizes to ll cache lines quickly. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mcf5206e integrated coldfire?microprocessor product brief 5 mcf5206e overview 1.1.4 internal sram the 8-kbyte on-chip sram provides one clock-cycle access for the coldfire core. the sram can store processor stack and critical code or data segments to maximize performance. 1.1.5 dram controller the mcf5206e dram controller provides a glueless interface for up to 2 banks of dram, each of which can range from 128 kbytes to 256 mbytes. the controller supports an 8-, 16-, or 32-bit data bus. a unique addressing schemes allows for increases in system memory size without rerouting address lines and rewiring boards. the controller operates in fast page or regular mode and supports extended-data-out (edo) drams. 1.1.6 mac module the mac unit provides high performance digital signal processing capabilities for the mcf5206e. integrated as an execution unit in the processor?s operand execution pipeline, the mac unit implements a three-stage arithmetic pipeline with sustained instruction issue rate of one mac cycle for 16x16 operations (while also supporting 32x32 operations). the mac opcodes provide a full feature set of extensions to the standard coldfire instruction set for signed and unsigned operands. in addition to executing the mac-speci c instructions, this unit also performs all integer multiply opcodes, providing higher performance for this class of operation. 1.1.7 dma controller the mcf5206e provides two fully programmable dma channels for quick data transfer (32 bits, with packing and unpacking supported). each channel has an external request pin associated with it. single and dual address mode is supported with the ability for program bursting and cycle stealing. with auto-alignment enabled, ef cient block transfers of up to 128 bits can be achieved. 1.1.8 dual uart modules the uart modules contain independent receivers and transmitters that are clocked by the uart internal timer. this timer is clocked by the system clock or an external clock supplied by the tin pin. data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity, and as many as two stop bits in 1/16 increments. four-byte receive buffers and 2-byte transmit buffers minimize cpu service calls. the uart modules also provide several error-detection and maskable-interrupt capabilities. modem support includes request-to-send (r ts ) and clear-to-send (cts ) signals. the system clock provides the clocking function via a programmable prescaler. select full duplex, autoecho loopback, local loopback, and remote loopback modes. the programmable uarts can interrupt the cpu on various normal or error condition events. 1.1.9 dual timer module the timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer for use in any of the three modes. one mode captures the timer value with an external event; another mode triggers an external signal or interrupts the cpu when the timer reaches a set value, while a third mode counts external events. the timer unit has an 8-bit prescaler that allows programming of the clock input f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6 mcf5206e integrated coldfire?microprocessor product brief motorola mcf5206e overview frequency, which is derived from the system clock. the programmable timer-output pin generates either an active low-pulse or toggles the output. 1.1.10 motorola bus (m-bus) module the m-bus interface is a two-wire, bidirectional serial bus that exchanges data between devices and is compatible with the i 2 c bus standard. the m-bus minimizes the interconnection between devices in the end system and is best suited for applications that need occasional bursts of rapid communication over short distances among several devices. bus capacitance and the number of unique addresses limit the maximum communication length and the number of devices that can be connected. 1.1.11 system interface the mcf5206e processor provides a glueless interface to 8-, 16-, and 32-bit port size sram, rom, and peripheral devices with independent programmable control of the assertion and negation of chip-selects and write-enables. programmable address and data-hold times can be extended for a compatible interface to external devices and memory. the mcf5206e also supports bursting roms. 1.1.11.1 external bus interface the bus interface controller transfers information between the coldfire core and memory, peripherals, or other masters on the external bus. the external bus interface provides as much as 28 bits of address bus space, a 32-bit data bus, and all associated control signals. this interface implements an extended synchronous protocol that supports bursting operations. for nonsynchronous external memory and peripherals, the mcf5206e processor provides an alternate asynchronous bus transfer acknowledgment signal. simple two-wire request/acknowledge bus arbitration between the mcf5206e processor and another bus master, such as the dma device, is glueless with arbitration handled internal to the mcf5206e processor. alternately, an external bus arbiter can control more complex three-wire (request, grant, busy) multiple-master bus arbitration, allowing overlapped bus arbitration with one clock-bus handovers. 1.1.11.2 chip selects eight programmable chip select outputs provide signals that enable external memory and peripheral circuits for automatic wait-state insertion. these signals also interface to 8-, 16-, 32-bit ports. in addition, other external bus masters can access chip selects. the other four chip-selects are multiplexed with a[27:24] of the address bus and four write-enable signals. the base address, access permissions, and timing waveforms are all programmable using con guration registers. except for fast page mode, all operations are available to other external bus masters. the dram controller can generate ras and cas for an external master and can continue to generate refresh requests. 1.1.11.3 8-bit parallel port interface an 8-bit general-purpose programmable parallel port serves as either an input or output on a bit-by-bit basis. the parallel port is multiplexed with the pst[3:0] and ddata[3:0] debug signals. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mcf5206e integrated coldfire?microprocessor product brief 7 mcf5206e overview 1.1.11.4 interrupt controller the interrupt controller provides user-programmable control of 3 or 7 external interrupt to any one of 7 interrupt levels and 4 priority levels. the 3 external interrupt signals can be con gured as either xed interrupt levels 1, 4, and 7, or as a 7-level encoded interrupt. the external interrupts can also be programmed to any one of the four priority levels within the respective interrupt levels. 1.1.11.5 system protection the mcf5206e processor contains a 16-bit software watchdog timer with an 8-bit prescaler. the programmable software watchdog timer provides either a level 7 interrupt or a hardware reset on timeout. the mcf5206e processor also contains a reset status register that indicates the cause of the last reset. 1.1.11.6 jtag to help with system diagnostics and testing during manufacture, the mcf5206e processor includes dedicated user-accessible test logic that complies with the ieee 1149.1 standard for boundary scan testability, often referred to as joint test action group, or jtag. for more information, refer to the ieee 1149.1 standard. 1.1.12 system debug interface the coldfire interface supports real-time trace and background debug mode. a 4-pin background debug mode (bdm) interface provides system debug. the bdm is a superset of the bdm interface provided on motorola?s 683xxx family of parts. in real-time trace, 4 status lines provide information on processor activity in real time (pst pins). a 4-bit wide debug data bus (ddata) displays operand data, which helps track the machine?s dynamic execution path as the change-of- ow instructions execute. these signals are multiplexed with the 8-bit parallel port for application development which does not use real-time trace. 1.1.13 system diagrams this section includes system and pinout diagrams. figure 2 shows the system of the mcf5206e device. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8 mcf5206e integrated coldfire?microprocessor product brief motorola mcf5206e overview . figure 2. mcf5206e system diagram system bus controller jtag port bus debug module coldfire core 4 kbyte instruction mac h/w divide 8 kbyte sram st a a t a tea irq7 / ipl2 tt[1:0] at m siz[1:0] r/w a[23:0] d[31:0] cs [3:0] cs [7:4] a[27:24]/ we [3:0]/ ras [1:0] cas [3:0] dramw br bg bd tck tdo/dso tms/bkpt tsi/dsi trst /dsclk hiz m-bus (i 2 c] module dual timer module dma controller scl sda txd1 rxd1 r ts1 cts1 txd2 rxd2 cts2 tin[1:0]/dreq0 clk interface interrupt controller clock tout[1:0]/dreq1 ts r ts2 /rst o rsti dram controller duart serial i/o chip selects parallel i/o port pst[3:0] pp[7:0] ddata[3:0] cache mtmod irq4 / ipl1 irq1 / ipl0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mcf5206e integrated coldfire?microprocessor product brief 9 mcf5206e overview figure 3 shows the mcf5206e pinout that is supplied in a 160-pin plastic quad at pack. figure 3. mcf5206e pinout diagram a26/cs 6/we 11 gnd aa25/cs 6/cs5/we a24/cs4/w e31 vdd a23 a22 gnd a21 a2o vdd a19 a18 vss a17 a16 vdd a15 a4 gnd a13 a12 vdd a11 a10 gnd a9 a8 vdd a7 a6 a5 a14 vdd a2 a3 gnd a1 a0 gnd d31 dram w vdd cas 3 cas 2 ca s1 gnd cas0 ras1 ras0 vdd bg bd br gnd irq1/ipl0 irq4/ipl irq7/ipl2 a t a vdd rst tea ts t a gnd r/w siz1 vdd siz0 at m tt1 tt0 cs 2 vdd cs0 a27/cs7/w e0 d30 cs3 cs 1 gnd d29 gnd d28 d27 d26 vdd d25 d24 d23 gnd d22 d21 d20 vdd d19 d18 d17 gnd d16 d15 d14 vdd d13 d12 d11 gnd d10 d9 d8 vdd d7 d6 d5 gnd d4 d3 d2 vdd d1 d0 trst /dsclk tck gnd tdo/dso hiz tdi/dsl tms/bkpi vdd jt a g gnd gnd cts 2 r ts2/r tso gnd clk rxd2 txd2 cts 1 r ts 1 vdd rxd1 txd1 dreq 0/tin0 tin1 gnd dreq 1/toui0 tout1 sda scl vdd pp7/pst3 pp6/pst2 pp5/pst1 pp4/pst0 gnd pp3/ddata3 pp2/ddata2 pp1/ddata1 ppo/ddata0 vdd 1 160 mcf5206e top view f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
10 mcf5206e integrated coldfire?microprocessor product brief motorola mcf5206e overview 1.1.14 qfp packages and operating frequencies table 1 identi es the packages and operating frequencies available for the mcf5206e processor. 1.1.15 document availability table 2 provides information on documentation available for the mcf5206e microprocessor. 1.1.16 development tools development tools for the mcf5206e processor consist of a complete suite of compilers and debuggers available from third-party developers, as shown in table 3. any development tool that generates code for the motorola coldfire mcf5206 can do the same for the mcf5206e processor. table 1. mcf5206e package/frequency availability package frequency temperature plastic quad flat pack 160 lead 40, and 54 mhz 0 to 70 c plastic quad flat pack 160 lead 40 mhz -40 to +85 c table 2. document availability document order number document title MCF5206EPB/d mcf5206e integrated microprocessor product brief mcf5206eum/d mcf5206e user?s manual cfprm/d coldfire family programmer?s reference manual table 3. development tools company name company phone number availability compliers/debuggers diab data 415-571-1700 now software development systems 708-368-0400 now rtos integrated systems 408-542-1781 now embeded system product 617-828-5588 now wind river systems 510-748-5588 now emulators yokogawa/orion instruments 408-747-0440 now embeded support tools (est) 617-828-5588 now noral micrologics 508-647-1013 lauterbach 508-620-4521 now microtek 503-645-7333 now f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mcf5206e integrated coldfire?microprocessor product brief 11 mcf5206e overview 1.1.17 revision history logic analyzers hewlett-packard (preprocessors only) 719-590-2558 now development boards order number m5206 ean now table 4. revision history revision date changes rev 1 1998 initial release rev 2 1/2002 new product brief format. rev 2.1 3/2002 in the system diagram on page 8: added mtmod signal to jtag block. corrected signal direction arrow on atm pin to indicate output. corrected signal direction arrow on cs[7:4]/a[27:24]/we[3:0] pins to indicate input/output changed interrupt controller pins names to irq7/ipl2,irq4/ipl1, irq1/ipl0. corrected signal direction arrow on tt[1:0] signals to indicate output. added revision history section. table 3. development tools (continued) company name company phone number availability f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MCF5206EPB/d how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre, 2 dai king street tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors document comments: fax (512) 933-2625 attn: tecd applications engineering information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and speci?ally disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical parameters which may be provided in motorola data sheets and/or speci?ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?ypicals must be validated for each customer application by customers technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark of?e. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/af?mative action employer. ?motorola, inc. 2002 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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